#hiring #visaprovided *Lead Engineer - Static Timing Analysis/Timing Closure (5-18 yrs) Overseas/International/Bangalore/UK/Sweden (Semiconductor/VLSI/EDA)*, New Delhi, *India* #helpinghands #opentowork #jobopportunity #jobseeking #lookingforjob #jobchange Candidate has to be present in IND, to apply *Apply* : https://ift.tt/3nwgoaK #newdelhi #india #helpinghands #opentowork #jobs #jobseekers #recruiting #recruitment #jobsnearme *Visa can be sponsored,for the successful candidate*

WORK PERMIT / VISA SPONSORED :

- Expertise in debugging STA timing constraints

- Lead SoC Front End Implementation Team working across different geographies.

- Mentor and guide Juniors on all technical aspects of SoC Timing, Block timing & Synthesis and PPA targets.

- Manage multiple stakeholders in the Project e.g. PD, DFT etc.

- Should be able to handle conformal ECO generation independently.

- Strong Knowledge on power aware synthesis and physical aware synthesis.

- Expertise in Perl/ Tcl / Python scripting

- Prior experience in formal verification for RTL 2 gates and gates2gates

- Must have worked on UPF 2.0 based power aware equivalence checking using Conformal.

- Expertise in debugging PA-FV failures

- Expertise in Low power synthesis on smaller blocks and subsystems using DC/Genus

PLEASE CLICK MESSAGE BELOW, TO APPLY

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